A very common gate array 10 is shown in FIG. 1, namely, a plurality of AND gates 12-14 driving an OR gate 16. The AND gates 12-14 have a plurality of inputs 18-24. An inverter 26 inverts input 18. Only two AND gates are shown. and each has only two inputs, and only one input is inverted, t8 but, in practice, rather large numbers of AND gates, inputs, and inverters may be supported. With a sufficiently large number of AND gates, inputs, and inverters on selected inputs, any reasonable Boolean output can be produced.
FIG. 2 shows the inverse 28 of array 10, with the AND gates 12-14 being replaced with OR gates 30-32, the OR gate 16 being replaced with an AND gate 34, and the inputs 18-24 being replaced with inputs 36-42. Input 36, corresponding to input 18, does NOT include an inverter corresponding to inverter 26. Inputs 38-42, corresponding to inputs 20-24, DO include inverters 44-48. If identical signals are applied to inputs 18-24 as are applied to inputs 36-42, the output of gate 34 will be the inverse of the output of gate 16.
Unfortunately, all of the gates are subject to failure, and this failure may be difficult to detect. FIG. 3 shows the conventional way: triplicate array 10, apply the same inputs 18-24 to each array, and apply the outputs of the arrays to a voting circuit 50. If all three inputs to the voting circuit 50 are the same, that common input is the output of the voting circuit 50. If they disagree, then the majority input is the voting circuit's output, and the array producing the minority input is marked for possible replacement. If desired, one or more of the arrays 10 may be replaced with its inverse 28, and the voting circuit 50 modified accordingly.
The conventional method produces reliability at the expense of tripling the cost, bulk, weight, and power consumption of the array 10. It is desirable to eliminate. or at least reduce, this tripling.